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inverted CERN School of Computing 2008 3-5-March 2008, CERN

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Towards Reconfigurable High-Performance Computing

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Reconfigurable HPC II - HW Design Methodology,
Theory & Tools

   

Tuesday 4 March

 

11:30-12:25

Lecture 8

Reconfigurable HPC II - HW Design Methodology,
Theory & Tools

Manfred Muecke

This lecture will first focus on existing tools for making use of FPGAs as number crunchers and will give examples of existing solutions. It will then discuss limitations and how they could be overcome.
Important topics:

  • Old attempts and current tools

  • About levels of HW abstraction

  • What is higher-level synthesis?

  • Examples from HPC and HEP

Audience
This lecture is intended for students seeking deeper understanding of hardware design description issues in general and when using FPGAs as number crunchers understanding of programming languages and basic compiler technology will be helpful.

Pre-requisite

This lecture builds upon the preceding lectures "6. Platforms III - Programmable Logic" and "7. Reconfigurable HPC I - Introduction".

While not necessarily being a required prerequisite for lecture 9 and 10, it motivates why going beyond existing tools is important.

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